1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a three-dimensional memory cell array where memory cells with two terminals having a nonvolatile variable resistive element are aligned in a three-dimensional matrix where the first direction, second and third direction are perpendicular to each other, as well as a manufacturing method for the same, and in particular, to a nonvolatile semiconductor memory device where the variable resistive element with two terminals that forms the memory cells reversibly changes between two or more different resistive states determined by the electrical resistance between the two terminals, and the states reversibly change when a voltage is applied and can be held in a nonvolatile manner, as well as a manufacturing method for the same.
2. Description of the Related Art
Flash memories, which are inexpensive nonvolatile memories having a large capacity that can store data even with the power turned off, are coming more widely into use together with the spread of mobile devices, such as portable electronics. In recent years, however, the limit as to how far flash memories can be miniaturized has become evident, and nonvolatile memories, such as MRAMs (magnetoresistance variable memories), PCRAMs (phase variable memories), CBRAMs (solid electrolyte memories) and RRAMs (resistance variable memories), have been in development full steam. From among these nonvolatile memories, RRAMs have been drawing attention because of their advantages, such as the fact that they make high speed rewriting possible, simple binary transition metal oxides can be used as the material, making fabrication easy, and they are highly compatible with existing CMOS processes.
From among memory devices formed of memory cells having variable resistive elements with two terminals, such as RRAMs, the combination of a memory cell structure and memory cell array structure that makes the greatest capacity possible provides a cross-point type memory cell array where 1R type memory cells each formed of a single variable resistive element are provided at the intersections between perpendicular wires. 1R type memory cells do not have any element that limits the current flowing through the variable resistive element, and therefore, can easily form a three-dimensional memory cell array where a number of layers of cross point type memory cell arrays are layered on top of each other (see for example US Unexamined Patent Publication 2005/0230724). However, 1R type memory cells do not have a current limiting element, and a parasitic current (leak current) flows through memory cells connected to unselected wires other than the memory cell formed between the two selected wires, and therefore, the parasitic current overlaps with the readout current that flows through the selected memory cell, and a problem arises, such that it becomes difficult, or impossible, to detect the readout current.
Measures against parasitic currents in 1R type memory cells include a method for providing a 1T1R type memory cell structure by connecting transistors to the variable resistive elements in series, and a method for providing a 1D1R type memory cell structure by connecting current limiting elements, such as diodes or barristers, to the variable resistive elements in series. Though 1T1R type memory cells are excellent in terms of controllability because it is possible to control the strength and direction of the current that flows through the variable resistive elements, they occupy a large area and cannot easily provide a multilayer structure, and therefore, the memory capacity is largely limited by the chip area and design rules. Meanwhile, 1D1R type memory cells can provide unit elements with a minimal area due to their cross point structure by optimizing the process, and as shown in Japanese Unexamined Patent Publication 2009-4725, for example, multiple layers are also possible, and thus, they are appropriate for large capacity.
In the case where a three-dimensional memory cell array is formed by providing multiple layers of conventional cross point type memory cell arrays, however, the photolithographic steps of forming patterns with a minimal size using an expensive state of the art stepper increase in proportion to the number of layers, and therefore, the cost is high when there are a large number of layers.
Furthermore, irrespectively of whether the memory cell array has a two-dimensional structure or a three-dimensional structure, a decoder for writing in and reading out information in memory cells with certain addresses in the memory cell array is required. In the case where conventional cross point type memory cell arrays are provided in multiple layers, as shown in FIGS. 5 to 7 in Japanese Unexamined Patent Publication 2009-4725, for example, a circuit for two-dimensionally decoding at least the word lines or the bit lines becomes necessary, and the circuit structure of the decoder becomes complex and occupies a large area, and thus the cost of the chip increases, because each of the word lines and the bit lines is aligned two-dimensionally, as well as in the direction of the layer, in the three-dimensional structure, though each of the word lines and bit lines is aligned one-dimensionally; that is, in one direction, in the two-dimensional structure.
Accordingly, a new memory cell array structure and a simple decoder circuit structure where 1D1R type memory cells can be used and it is not necessary to increase the number of masking steps together with the number of layers are required in order to implement an inexpensive RRAM having a large capacity.